document no. 70-0246-03 www.psemi.com page 1 of 9 ?2008 peregrine semiconductor corp. all rights reserved. rf1 rf2 ctrl ls rfc 50 ? 50 ? cmos control driver esd esd 16-lead 3x3 mm qfn figure 2. package type the PE42552 rf switch is designed for use in test/ate, cellular and other wireless applications. this broadband general purpose switch maintains excellent rf performance and linearity from dc through 7500 mhz. the PE42552 integrates on-board cmos control logic driven by a single-pin, low voltage cmos control input. it also has a logic select pin which enables changing the logic definition of the control pin. additional features include a novel user defined logic table, enabled by the on-board cmos circuitry. the PE42552 also exhibits outstanding isolation of 44 db at 7500 mhz, fast settling time, and is offered in a tiny 3x3 mm qfn package. the PE42552 is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt ultracmos? rf switch dc - 7500 mhz product description figure 1. functional diagram PE42552 features ? harp?-technology-enhanced ? eliminates gate and phase lag ? no insertion loss or phase drift ? fast settling time ? high linearity: 65 dbm iip3 ? low insertion loss: 0.65 db at 3.0 ghz, 0.85 db at 6.0 ghz, 1.0 at 7.5 ghz ? high isolation of 47 db at 3.0 ghz, 44 db at 7.5 ghz ? 1 db compression point: +34.5 dbm typ. ? logic select pin to invert logic control ? high esd: 1000 v hbm ? absorptive switch design ? standard 3x3 mm qfn package table 1. target electrical specifications temp = 25c, v dd = 3.3v , v ss = 0v / -3.3v parameter conditions min typical max units operation frequency mhz 9 khz 7.5 ghz insertion loss 9 khz 3000 mhz 6000 mhz 7500 mhz 0.6 0.65 0.85 1.0 0.7 0.8 1.0 1.22 db db db db isolation ? rf1 to rf2 3000 mhz 6000 mhz 7500 mhz 45 32 25 47 34 28 db db db isolation ? rfc to rfx 3000 mhz 6000 mhz 7500 mhz 44 49 37 47 55 44 db db db return loss 3000 mhz 6000 mhz 7500 mhz 20 25 15 db db db settling time 50% ctrl to 0.05 db final value (-40 to +85 c) rising edge 50% ctrl to 0.05 db final value (-40 to +85 c) falling edge 9 15 11 45 switching time 50% ctrl to 90% or 10% of final value (-40 to +85 c) 5 7 s input 1 db compression 800 mhz 7500 mhz 32 34.5 34 dbm dbm input ip3 7500 mhz 65 dbm input ip2 7500 mhz 100 dbm s s
product specification PE42552 page 2 of 9 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0246-03 ultracmos? rfic solutions table 2. pin descriptions table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. figure 3. pin configuration (top view) pin no. pin name description 2 rf1 rf port 1 1, 3, 4, 5, 6, 8, 9, 10, 12 gnd ground 7 rfc rf common 11 rf2 rf port 2 13 v ss negative supply voltage or gnd connection (note 1) 14 ctrl cmos level: 15 ls logic select - used to determine the definition for the ctrl pin (see table 5) 16 v dd nominal 3.3 v supply connection table 5. control logic truth table gnd gnd rfc gnd gnd rf1 gnd gnd gnd gnd rf2 gnd vss ctrl ls vdd 1 16 15 14 13 12 11 10 9 5 6 7 8 2 3 4 exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input except for ctrl and ls inputs -0.3 v dd + 0.3 v v ctrl voltage on ctrl input 4.0 v v ls voltage on ls input 4.0 v t st storage temperature range -65 150 c p in input power: 9 khz 1 mhz 1 mhz 7.5 ghz fig. 4,5 30 dbm dbm v esd esd voltage (hbm) 1 esd voltage (machine model) 1000 100 v v table 3. operating ranges parameter min typ max units v dd positive power supply voltage 3.0 3.3 3.6 v v ss negative power supply voltage (external power supply used) -3.6 -3.3 -3.0 v i dd power supply current (v ss = 0v, temp = +85 c) 15 120 a control voltage high 0.7xv dd v control voltage low 0.3xv dd v rf power in 1 (p in ): 9 khz 1 mhz 1 mhz 7.5 ghz fig. 4,5 30 dbm dbm v ss negative power supply voltage (internal power supply used) -0.1 0.0 0.0 v i ss negative supply (v ss = -v dd , temp = 25 c) -10 -40 a t op operating temperature range -40 25 85 c note: 1. please consult low frequency graphs on page 3 for recommended operating power level. note: 1. human body model (hbm, mil_std 883 method 3015.7) moisture sensitivity level the moisture sensitivity level rating for the PE42552 in the 16-lead 3x3mm qfn package is msl1. logic select (ls) the logic select feature is used to determine the definition for the ctrl pin. note: 1. use vss (pin 13, vss = -vdd) to bypass and disable internal negative voltage generator. connect vss (pin 13) to gnd (vss = 0v) to enable internal negative voltage generator. switching frequency the PE42552 has a maximum 25 khz switching rate when the internal negative voltage generator is used (pin 13=gnd). the rate at which the PE42552 can be switched is only limited to the switching time (table 1) if an external negative supply is provided at (pin13=vss). ls ctrl rfc-rf1 rfc-rf2 0 0 off on 0 1 on off 1 0 on off 1 1 off on spurious performance the typical spurious performance of the PE42552 is -116 dbm when vss=0v (pin 13 = gnd). if further improvement is desired, the internal negative voltage generator can be disabled by setting vss = -vdd.
product specification PE42552 page 3 of 9 document no. 70-0246-03 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. -12 -10 -8 -6 -4 -2 0 2 4 6 8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) input power (dbm) upper power limit 0 5 10 15 20 25 30 1 10 100 1000 freq (khz) operating power offset (db) figure 5 shows how the power limit in figure 4 will increase with frequency. as the frequency increases, the contours and maximum power limit curve will increase with the increase in power handling shown on the curve. figure 4. maximum operating power limit vs. vdd and input power @ 9 khz figure 5. operating power offset vs. frequency (normalized to 9khz) figure 4 provides guidelines of how to adjust the vdd and input power to the 42552 device. the upper limit curve represents the maximum input power vs vdd recommended for this part. to allow for sustained operation under any load vswr condition, max power should be kept 6db lower than max power in 50 ohm. power handling examples example 1: maximum power handling at 100khz, z=50 ohms, vswr 1:1, and vdd=3v ? the power handling offset for 100khz from fig. 5 is 10db ? the max power handling at vdd = 3v is 5.5db from fig. 4 ? derate power under mismatch conditions ? total maximum power handling for this example is 10db + 5.5db = 15.5dbm low frequency power handling: z l = 50 ?
product specification PE42552 page 4 of 9 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0246-03 ultracmos? rfic solutions -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0123456789 frequency [ghz] insertion loss [-db] 3.0 v 3.3 v 3.6 v -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0123456789 frequency [ghz] insertion loss [-db] rf1 path rf2 path -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0123456789 frequency [ghz] isolation [-db] +25deg c +85deg c -40deg c -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0123456789 frequency [ghz] isolation [-db] 3.0 v 3.3 v 3.6 v -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0123456789 frequency [ghz] isolation [-db] +25deg c +85deg c -40deg c -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0123456789 frequency [ghz] insertion loss [-db] +25deg c +85deg c -40deg c figure 9. isolation: active port to isolated port @ 3.3 v figure 8. insertion loss: rfx @ 25 c figure 6. nominal insertion loss: rf1, rf2 figure 7. insertion loss: rfx @ 3.3 v performance plots: temperature = 25 c, v dd = 3.3 v unless otherwise indicated figure 10. isolation: active port to isolated port @ 25 c figure 11. isolation: rfc to isolated port @ 3.3 v
product specification PE42552 page 5 of 9 document no. 70-0246-03 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. 0 10 20 30 40 50 60 70 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 1.e+09 1.e+10 frequency [hz] iip3 [dbm] 3.0 v 3.3 v 3.6 v -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0123456789 frequency [ghz] isolation [-db] 3.0 v 3.3 v 3.6 v -35 -30 -25 -20 -15 -10 -5 0 0123456789 frequency [ghz] return loss [-db] 3.0 v 3.3 v 3.6 v -30 -25 -20 -15 -10 -5 0 0123456789 frequency [ghz] return loss [-db] +25deg c +85deg c -40deg c figure 14. return loss at active port @ 25 c figure 15. return loss at active port @ 3.3 v performance plots: temperature = 25 c, v dd = 3.3 v unless otherwise indicated figure 12. isolation: rfc to isolated port @ 25 c figure 13. iip3: third order distortion from 10khz - 7.5ghz
product specification PE42552 page 6 of 9 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0246-03 ultracmos? rfic solutions through line l1 was inductor 1 2 j5 142-0761-881/891 1 2 j1 142-0761-881/891 1 2 j3 142-0761-881/891 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j4 header 14 1 2 j2 142-0761-881/891 c1 22pf r1 dni c2 22pf r2 dni c3 22pf 1 2 j6 142-0761-881/891 r3 dni c4 68pf 9 gnd 10 gnd 11 rf2 12 gnd 13 vss 14 ctrl 15 ls 16 vdd 1 gnd 3 gnd 2 rf1 4 gnd 5 gnd 6 gnd 8 gnd 7 rfc u1 qfn50p3x3-16p r4 0 ohm l1 0 ohm ls rf2 ctrl vdd vss rf1 rfc evaluation kit the spdt switch ek board was designed to ease customer evaluation of peregrine?s PE42552. the rf common port is connected through a 50 ? transmission line via the top sma connector, j1. rf1, rf2, rf3 and rf4 are connected through 50 ? transmission lines via sma connectors j3, j5, j2 and j4, respectively. a through 50 ? transmission is available via sma connectors j6 and j7. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the evaluation kit board is constructed of four metal layers. the dual clad top rf layer is rogers ro4003 material with an 8 mil rf core and er = 3.55. the other two dielectric layers are fr4 for dc control and overall board strength with an cumulative board thickness of 60 mils. the rf transmission lines were designed using a grounded co-planar waveguide with a linewidth of 15 mils and gap of 10 mils. figure 16. evaluation board layouts figure 17. evaluation board schematic peregrine specification 102/0404 peregrine specification 101/0334
product specification PE42552 page 7 of 9 document no. 70-0246-03 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. 16-lead 3x3 mm qfn figure 18. package drawing (mm) qfn 3x3 mm a max 0.800 nom 0.750 min 0.700
product specification PE42552 page 8 of 9 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0246-03 ultracmos? rfic solutions 16-lead 3x3 mm qfn figure 19. tape and reel specifications table 6. ordering information tape feed direction order code part marking description package shipping method PE42552mlib 42552 PE42552g-16qfn 3x3mm-75a green 16-lead 3x3mm qfn bulk or tape cut from reel PE42552mlib-z 42552 PE42552g-16qfn 3x3mm-3000c green 16-lead 3x3mm qfn 3000 units / t&r ek42552-02 PE42552-ek PE42552-16qfn 3x3mm-ek evaluation kit 1 / box device orientation in tape top of device pin 1
product specification PE42552 page 9 of 9 document no. 70-0246-03 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at an y time without notice in order to supply the best possible product. product specification the data sheet contains final dat a. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a dcn (document change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which persona l injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental dam ages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. hi-rel and defense products americas: tel: 858-731-9453 europe, asia pacific: 180 rue jean de guiramand 13852 aix-en-provence cedex 3, france tel: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213
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